The semiconductor industry continuously strives to reduce the size and cost of integrated circuits. It is common in the semiconductor art to use layers of metal, polysilicon, or another conductor to conduct current between various semiconductor structures with an integrated circuit, and to external terminals for the integrated circuit, by means of conductive vias. One method for measuring the performance of an integrated circuit uses the maximum clock speed at which the circuit operates reliably, which depends on how fast transistors can be switched and how fast signals can propagate.
One particular problem confronting the semiconductor industry is that, as integrated circuit scaling continues, the performance improvement is limited by the signal delay time attributable to interconnects in the integrated circuit. That is, the capacitance at metal interconnects increases as the density of the integrated circuit increases. According to one definition, integrated circuit interconnects are three-dimensional metal lines with submicrometer cross sections surrounded by insulating material. One definition of an interconnect delay is the product of the interconnect resistance (R) and the parasitic capacitance (C) for the interconnect metal to the adjacent layers. Because of the progressive scaling, the parasitic capacitance (C) has significantly increased due to closer routing of wires, and the interconnect resistance (R) has significantly increased due to a continuous reduction of the wire section.
The following approximations for various generations of integrated circuit technology illustrates this problem. For example, the delay in 0.7 μm technology is about 500 ps, in which about 200 ps seconds are attributable to gate delays and about 300 ps are attributable to interconnect delays. The delay in 0.18 μm technology is about 230 ps, in which about 30 ps are attributable to gate delays and about 200 ps are attributable to interconnect delays. As integrated circuit scaling continues, it is desirable to lower the interconnect RC time constant by using metals with a high conductivity. One high conductivity metal used to lower the RC constant is copper. The use of copper in 0.18 μm technology improves the interconnect delays to about 170 ps. However, even though the delay attributable to the gates continues to decrease as scaling continues beyond the 0.18 μm technology, the overall delay increases significantly because the interconnect delay is significantly increased. It has been estimated that as much as 90 percent of the signal delay time in future integrated circuit designs may be attributable to the interconnects and only 10 percent of the signal delay may be attributable to transistor device delays. As such, it is desirable to lower the interconnect RC time constant by using materials with a low dielectric constant (k).
One direction for developing low-k dielectrics incorporates air into dielectrics to make them porous. The dielectric constant of the resulting porous material is a combination of the dielectric constant of air (k≈1) and the dielectric constant of the dielectric material. As such, it is possible to lower the dielectric constant of a low-k dense material by making the dielectric material porous. However, some methods for providing porous dielectric materials involve rather complex processing steps that are difficult to consistently perform, which increases the time and cost of processing.
Therefore, there is a need in the art to provide a system and method that improves integrated circuit performance by reducing the interconnect RC time constant. There is a need in the art to provide a low-k dielectric insulator for the interconnects that is easily and consistently prepared in a timely and cost-effective manner.